1. Field of the Invention
The present invention is generally related to a method and device for accessing a frame memory, particularly, to an accessing technique of a frame memory integrated within a display panel driver adopting a sub-field addressing method.
2. Description of the Related Art
The sub-field addressing method is a typical drive sequence for achieving a gray scale in pixels of a plasma display panel. The sub-field addressing method divides each frame into a plurality of sub-fields, and each of the sub-fields is further divided into an address period and a sustain period. Each pixel is activated or turned on during the sustain period(s) of one or more selected sub-fields in response to the intensity thereof, and this selective activation achieves a gray scale in each pixel. In order to emit light from a given pixel site during a given sub-field, the pixel site is selected to receive a write address pulse during the associated address period, and a sustain voltage is applied to the selected pixel site to cause an emission of light therefrom during the associated sustain period.
FIG. 1 shows a drive sequence to achieve a 16 gray scale using a sub-field addressing method. The drive sequence divides each frame into four sub-fields SF1 to SF4. The length of each of the four sub-fields is different. The first sub-field SF1 has a sustain period with eight sustain cycles, each corresponding to a sustain pulse, the second sub-field has four sustain cycles, the third sub-field has two sustain cycles, and the fourth sub-field has a sustain period with only one complete sustain cycle. The pixel site is activated during one or more of the sub-fields SF1 to SF4 selected in response to the intensity or the gray scale level of the pixel site to achieve a 16 (=24) gray scale. The number of available gray scale levels increases as an increase in the number of the sub-fields. In order to achieve a 256 gray scale, a frame is necessary to include eight sub-fields.
Implementing a sub-field addressing method requires appropriate allocation of sub-field data of each sub-field in a frame memory disposed within a display driver, where the sub-field data is representative of illumination or extinction of each pixel during each sub-field. FIG. 2A to FIG. 2D illustrates an exemplary memory map of a frame memory adapted for the sub-field addressing method. The frame memory stores image data for two frames to achieve a double buffering technique. This requires the frame memory to have a memory capacity more than 96 Mbits for driving a display panel in accordance with the full color WXGA (wide extended graphics array) specification, which involves 1365×768 pixels with a 16 bit data word for each pixel. It should be noted that each line within the panel includes 1365 pixels, and the intensity of each pixel is represented by 16 data bits.
In order to satisfy this requirement, the frame memory includes a 128 Mbit synchronous dynamic random access memory with four 32 Mbit banks #1 to #4. The banks #1 and #2 are used for storing image data of odd-numbered frames, while the banks #3 and #3 are used for storing image data of even-numbered frames. Each of the banks #1 to #4 is organized as 4,096 rows by 256 columns by 32 bits. This means that each row within the banks has a capacity for storing sub-field data of two lines of pixels, and storing a complete set of sub-field data for a frame requires 192 rows in each of the two banks associated with the frame. Each banks includes 16 regions, which are respectively associated with 16 sub-fields. The row addresses over 3072 are not in use for the WXGA specification.
Write and read operations of the frame memory usually adopt different access sequences. The write operation into the frame memory is implemented in units of pixel lines, while the read operation is implemented in units of sub-fields. For the frame memory shown in FIGS. 2A through 2D, for example, the write operation begins with a sequential write of sub-field data of the 1st line for 1st through 16th sub-fields in the order of the sub-field number. A sequential write of sub-field data of the 2nd line then follows, a sequential write of sub-field data of the 3rd line then follows, and so force, until a sequential write of sub-field data of the 768th line is completed. The read operation, on the other hand, begins with a sequential read of sub-field data of the 1st through 768th lines for the 1st sub-field. A sequential read for the 2nd sub-field then follows, a sequential read for the 3rd sub-field then follows, and so force, until the sequential read for the 16th sub-fields is completed.
FIG. 3 shows an exemplary access sequence of the frame memory shown in FIGS. 2A through 2D. FIG. 3 refers to symbols “Rd” and “Wr” as read and write operations of sub-field data of a certain line for a certain sub-field, respectively. Write sub-field data 902 of the 1st line for the 1st through 16th sub-fields are serially inputted to the frame memory in synchronization with a write horizontal sync signal 901, while read sub-field data 904 of the 1st through 16th lines for the 1st sub-fields are serially outputted from the frame memory in synchronization with a read horizontal sync signal 903. The read and write operations for the read and write sub-field data are alternately performed in synchronization with the read horizontal sync signal 903.
The access sequence shown in FIG. 3 has an advantage that it requires only a single port for a frame memory to exchange write and read sub-field data, that is, eliminates necessity for providing separated write and read ports within a frame memory. This advantageously reduces cost of frame memories.
Another advantage of the access sequence is its simplicity, and this feature ensures write and read operations of sub-field data for a given frame in the associated frame time.
Display drivers are desirably designed to allow the numbers of sub-fields of write and read image data to be independently adjustable, because this promotes the use of the same display driver for driving different display panels, and thereby reduces cost of display drivers through a mass production effect. This requirement has been enhanced by an increase in the number of sub-fields within a frame for improving image quality.
In addition, display drivers are desirably designed to achieve fast write operation to frame memories integrated therein. The aforementioned method and system suffer from a drawback that the write cycle time is restricted by the read cycle time, which is determined by the frame rate or the frame time.
3. Prior Art Documents
Japanese Unexamined Patent Application No. Jp-A 2001-215934 discloses a display driver for allowing users to select a desired image from among inputted images and to quickly switch images without causing deterioration of the images.
Japanese Unexamined Patent Application No. Ja-A-Heisei 10-260677 discloses a technique for allowing a display driver adopting a double buffer architecture to display a static image on the display screen without using special controller circuit. The display driver includes a pair of frame memories and a switching circuitry to achieve a double buffer technique. For displaying a static memory, the display driver disables the switching circuitry and reads out the same image data from selected one of the frame memories.
Japanese Unexamined Patent Application No. Jp-A-Heisei 10-268833 discloses a method and system for achieving fine resolution and gray scale without using a high speed frame memory. The method and system rearranges a bit frame in response to pixel positions and firing timings, and stores the rearranged bit frame into a plurality of frame memories so that the system are allowed to obtain the bit frame at a single read cycle. This effectively eliminates the necessity for using a high speed memory device as the frame memory.
Japanese Unexamined Patent Application No. Jp-A-Heisei 11-175024 discloses a plasma display system for achieving fine resolution and gray scale without using a high speed frame memory. Bit frames are allocated and stored into a frame memory in response to the positions of pixels associated therewith, and a dual port memory is used as the frame memory. This allows the frame memory to provide address drivers with address data without reordering. This effectively eliminates the necessity for using a high speed memory device as the frame memory.
Japanese Unexamined Patent Application No. Jp-A Heisei 8-194451 discloses an LCD (liquid crystal display) driver using a multi-line selection method (MLS method) for calculating a column line voltage in a short time with a low-speed DRAM. The disclosed LCD driver includes a pair of frame memories, one storing odd-numbered bit frames, and the other storing even-numbered bit frames. The associated pair of bit frames are successively transferred to from the frame memory to a column voltage calculating circuit.
Japanese Unexamined Patent Application No. Jp-A-Heisei 8-76713 discloses a technique for driving an electroluminescent display or a liquid crystal displays with a CRT (cathode ray tube) controller. The technique divides a display screen into a pair of regions. One of the regions is driven in response to image data received from a video memory. Image data for the remaining regions are transferred to associated frame memories, and remaining regions are driven in response to image data received from the frame memories.
Japanese Unexamined Patent Application No. Jp-A-Heisei 5-303477 discloses a display control system for reducing the time required for reading out data as less as possible while maintaining the extensibility of the system by previously storing the arrangement information of addresses for data required for processing.